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ICS8530DY-01 www.icst.com/products/hiperclocks.html rev. b august 8, 2001 1

ics8530-01 l ow s kew , 1- to -16 d ifferential - to -3.3v lvpecl f anout b uffer b lock d iagram p in a ssignment clk nclk q0 nq0 q1 nq1 q2 nq2 q3 nq3 q4 nq4 q5 nq5 q6 nq6 q7 nq7 q15 nq15 q14 nq14 q13 nq13 q12 nq12 q11 nq11 q10 nq10 q9 nq9 q8 nq8 hiperclocks? ,&6 f eatures ? 16 differential 3.3v lvpecl outputs ? clk, nclk input pair ? clk, nclk pair can accept the following differential input levels: lvds, lvpecl, lvhstl, sstl, hcsl ? maximum output frequency up to 500mhz ? translates any single-ended input signal to 3.3v lvpecl levels with a resistor bias on nclk input ? output skew: 75ps (maximum) ? part-to-part skew: 250ps (maximum) ? 3.3v output operating supply ? 0 c to 70 c ambient operating temperature ? industrial temperature information available upon request g eneral d escription the ics8530-01 is a low skew, 1-to-16 differen- tial-to-3.3v lvpecl fanout buffer and a mem- ber of the hiperclocks ? family of high perfor- mance clock solutions from ics. the clk, nclk pair can accept most standard differential input levels. the high gain differential amplifier accepts peak-to- peak input voltages as small as 150mv as long as the com- mon mode voltage is within the specified minimum and maxi- mum range. guaranteed output and part-to-part skew characteristics make the ics8530-01 ideal for those clock distribution appli- cations demanding well defined performance and repeatabil- ity. 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 v cco q11 nq11 q10 nq10 v ee q9 nq9 q8 nq8 v cco v cc clk v cco nq0 q0 nq1 q1 v ee nq2 q2 nq3 q3 vcco nclk v cco q15 nq15 q14 nq14 v ee q13 nq13 q12 nq12 v cco ics8530-01 v cco nq4 q4 nq5 q5 v ee nq6 q6 nq7 q7 v cco v cc 48-pin lqfp 7mm x 7mm x 1.4mm package body y package top view
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ics8530-01 l ow s kew , 1- to -16 d ifferential - to -3.3v lvpecl f anout b uffer t able 1. p in d escriptions t able 2. p in c haracteristics t able 3. f unction t able r e b m u ne m a ne p y tn o i t p i r c s e d , 4 2 , 4 1 , 1 1 , 1 8 4 , 8 3 , 5 3 , 5 2 v o c c r e w o p. v 3 . 3 o t t c e n n o c . s n i p y l p p u s t u p t u o 3 , 21 1 q n , 1 1 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 5 , 40 1 q n , 0 1 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 3 4 , 0 3 , 9 1 , 6v e e r e w o p. d n u o r g o t t c e n n o c . s n i p y l p p u s e v i t a g e n 8 , 79 q n , 9 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 0 1 , 98 q n , 8 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 3 1 , 2 1v c c r e w o p. v 3 . 3 o t t c e n n o c . s n i p y l p p u s e v i t i s o p 6 1 , 5 17 q n , 7 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 8 1 , 7 16 q n , 6 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 1 2 , 0 25 q n , 5 qt u p t u o. . s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 3 2 , 2 24 q n , 4 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 7 2 , 6 23 q n , 3 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 9 2 , 8 22 q n , 2 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 6 3k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 7 3k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 0 4 , 9 35 1 q n , 5 1 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 2 4 , 1 44 1 q n , 4 1 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 5 4 , 4 43 1 q n , 3 1 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 7 4 , 6 42 1 q n , 2 1 qt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t s r e f e r s t u p n is t u p t u o e d o m t u p t u o o t t u p n iy t i r a l o p k l ck l c n5 1 q u r h t 0 q5 1 q n u r h t 0 q n 01w o lh g i hl a i t n e r e f f i d o t l a i t n e r e f f i dg n i t r e v n i n o n 10 h g i hw o ll a i t n e r e f f i d o t l a i t n e r e f f i dg n i t r e v n i n o n 01 e t o n ; d e s a i bw o lh g i hl a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i n o n 11 e t o n ; d e s a i bh g i hw o ll a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i n o n 1 e t o n ; d e s a i b0h g i hw o ll a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i 1 e t o n ; d e s a i b1w o lh g i hl a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i l a i t n e r e f f i d e h t g n i r i w s e s s u c s i d h c i h w , 8 e r u g i f , 7 e g a p n o n o i t c e s n o i t a m r o f n i n o i t a c i l p p a e h t o t r e f e r e s a e l p : 1 e t o n . s l e v e l d e d n e e l g n i s t p e c c a o t t u p n i l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i k l c n , k l c 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k ? r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k ?
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ics8530-01 l ow s kew , 1- to -16 d ifferential - to -3.3v lvpecl f anout b uffer t able 4a. p ower s upply dc c haracteristics , v cc = v cco = 3.3v5%, t a = 0 c to 70 c a bsolute m aximum r atings supply voltage, v ccx 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, v o -0.5v to v cco + 0.5v package thermal impedance, ja 47.9 c/w storage temperature, t stg -65 c to 150 c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in th e dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended peri- ods may affect product reliability. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c / t u p n i 5 3 1 . 33 . 35 6 4 . 3v v o c c e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v i e e t n e r r u c y l p p u s r e w o p 0 2 1a m t able 4b. d ifferential dc c haracteristics , v cc = v cco = 3.3v5%, t a = 0 c to 70 c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i k l cv c c v = n i v 5 6 4 . 3 =0 5 1a k l c nv c c v = n i v 5 6 4 . 3 =5a i l i t n e r r u c w o l t u p n i k l cv c c v , v 5 6 4 . 3 = n i v 0 =5 -a k l c nv c c v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c ; e g a t l o v t u p n i e d o m n o m m o c 2 , 1 e t o n v e e 5 . 0 +v c c 5 8 . 0 -v v s i k l c n , k l c r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 1 e t o n c c . v 3 . 0 + v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o n h i . t able 4c. lvpecl dc c haracteristics , v cc = v cco = 3.3v5%, t a = 0 c to 70 c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov o c c 4 . 1 -v o c c 0 . 1 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov o c c 0 . 2 -v o c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 6 . 05 8 . 0v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n ? v o t o c c . v 2 -
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ics8530-01 l ow s kew , 1- to -16 d ifferential - to -3.3v lvpecl f anout b uffer t able 5. ac c haracteristics , v cc = v cco = 3.3v5%, t a = 0 c to 70 c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o m u m i x a m 0 0 5z h m t d p 1 e t o n ; y a l e d n o i t a g a p o r p ? z h m 0 0 51 2s n t ) o ( k s4 , 2 e t o n ; w e k s t u p t u o 5 7s p t ) p p ( k s4 , 3 e t o n ; w e k s t r a p - o t - t r a p 8 80 5 2s p t r e m i t e s i r t u p t u oz h m 0 5 @ % 0 8 o t % 0 20 0 30 0 7s p t f e m i t l l a f t u p t u oz h m 0 5 @ % 0 8 o t % 0 20 0 30 0 7s p c d oe l c y c y t u d t u p t u o7 40 53 5% . e s i w r e h t o d e t o n s s e l n u z h m 0 5 2 t a d e r u s a e m s r e t e m a r a p l l a . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c d a o l l a u q e h t i w d n a . s t n i o p s s o r c l a i t n e r e f f i d e h t t a . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n
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ics8530-01 l ow s kew , 1- to -16 d ifferential - to -3.3v lvpecl f anout b uffer p arameter m easurement i nformation f igure 1 - o utput l oad t est c ircuit scope qx nqx lvpecl v cc = 2v 5% v cco = 2v 5% v cc v cco v ee = -1.3v 0.135v f igure 2 - d ifferential i nput l evel v cmr cross points v pp clk nclk v ee v cc f igure 3 - o utput s kew t sk(o) qx nqx qy nqy
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ics8530-01 l ow s kew , 1- to -16 d ifferential - to -3.3v lvpecl f anout b uffer f igure 7 - odc & t p eriod pulse width t period t pw t period odc = clk, qx nclk, nqx f igure 6 - p ropagation d elay t pd clk nclk q0 - q15 nq0 - nq15 f igure 4 - p art - to -p art s kew qx nqx qy nqy part 1 part 2 t sk(pp) f igure 5 - i nput and o utput r ise and f all t ime clock inputs and outputs 20% 80% 20% 80% t r t f v swing
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ics8530-01 l ow s kew , 1- to -16 d ifferential - to -3.3v lvpecl f anout b uffer a pplication i nformation w iring the d ifferential i nput to a ccept s ingle e nded l evels figure 8 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref ~ v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the r atio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input c lock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. f igure 8 - s ingle e nded s ignal d riving d ifferential i nput r2 1k v cc clk_in + - r1 1k c1 0.1uf v_ref
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ics8530-01 l ow s kew , 1- to -16 d ifferential - to -3.3v lvpecl f anout b uffer p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics8530-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics8530-01 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 120ma = 415.8mw ? power (outputs) max = 30.2mw/loaded output pair if all outputs are loaded, the total power is 16 * 30.2mw = 483.2mw total power _max (3.465v, with all outputs switching) = 415.8mw + 483.2mw = 899mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125 c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used . assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 47.9 c/w per table 6 below. therefore, tj for an ambient temperature of 70 c with all outputs switching is: 70 c + 0.899w * 47.9 c/w = 113.1 c. this is well below the limit of 125 c this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67.8 c/w 55.9 c/w 50.1 c/w multi-layer pcb, jedec standard test boards 47.9 c/w 42.1 c/w 39.4 c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. table 6. thermal resistance ja for 48-pin lqfp, forced convection
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ics8530-01 l ow s kew , 1- to -16 d ifferential - to -3.3v lvpecl f anout b uffer 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 9. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cc - 2v. pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max - 2v))/r l ]*(v cc_max - v oh_max ) pd_l = [(v ol_max ? (v cc_max - 2v))/r l ]*(v cc_max - v ol_max ) for logic high, v out = v oh_max = v cc_max ? 1.0v using v cc_max = 2.625, this results in v oh_max = 1.625v for logic low, v out = v ol_max = v cc_max ? 1.7v using v cc_max = 2.625, this results in v ol_max = 0.925v pd_h = [(1.625v - (2.625v - 2v))/50 ? ]*(1v) = 20mw pd_l = [(0.925v - (2.625v - 2v))/50 ? ]*(1.7) = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30.2mw f igure 9 - lvpecl d river c ircuit and t ermination q1 v out v cco rl 50 v cco - 2v
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ics8530-01 l ow s kew , 1- to -16 d ifferential - to -3.3v lvpecl f anout b uffer r eliability i nformation t ransistor c ount the transistor count for ics8530-01 is: 930 t able 7. vs . a ir f low t able ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67.8 c/w 55.9 c/w 50.1 c/w multi-layer pcb, jedec standard test boards 47.9 c/w 42.1 c/w 39.4 c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
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ics8530-01 l ow s kew , 1- to -16 d ifferential - to -3.3v lvpecl f anout b uffer p ackage o utline - y s uffix t able 8. p ackage d imensions reference document: jedec publication 95, ms-026 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s c b b m u m i n i ml a n i m o nm u m i x a m n 8 4 a - -- -0 6 . 1 1 a 5 0 . 0- -5 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 7 1 . 02 2 . 07 2 . 0 c 9 0 . 0- -0 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d . f e r 0 5 . 5 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e . f e r 0 5 . 5 e c i s a b 0 5 . 0 l 5 4 . 00 6 . 05 7 . 0 0 - - 7 c c c - -- -8 0 . 0
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ics8530-01 l ow s kew , 1- to -16 d ifferential - to -3.3v lvpecl f anout b uffer t able 9. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pt n u o ce r u t a r e p m e t 1 0 - y d 0 3 5 8 s c i1 0 - y d 0 3 5 8 s c ip f q l d a e l 8 4y a r t r e p 0 5 2c 0 7 o t c 0 t 1 0 - y d 0 3 5 8 s c i1 0 - y d 0 3 5 8 s c il e e r d n a e p a t n o p f q l d a e l 8 40 0 0 1c 0 7 o t c 0

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